Technical Field
The present disclosure relates to the fabrication of nanometer-sized integrated circuit FET (field effect transistor) devices and, in particular, to methods of tuning performance of the FETs by incorporating selected molecular clusters.
Description of the Related Art
As technology nodes for transistors scale below 10 nm, maintaining control of various electrical characteristics in bulk semiconductor devices becomes increasingly more challenging. Such electrical characteristics include, for example, transistor threshold voltage and contact resistance. The threshold voltage of a transistor fundamentally governs the transition from an “off” state to an “on” state, and therefore dictates the switching speed and the off-state leakage current of the transistor. By tuning the threshold voltage of a transistor, integrated circuit designers can optimize transistor performance by balancing the need for fast switching speed with the need for low power consumption. For example, circuit designers may choose to place low threshold voltage (LVT) transistors, which are fast but leaky, specifically in critical circuit paths that have maximum delays. Slower, high threshold voltage transistors that have low leakage current in the off state can then be used in non-critical paths so that power consumption stays low. Thus, it is advantageous to be able to provide transistors on the same integrated circuit chip that have a range of threshold voltages. Contact resistance at the interface between the source and drain terminals of the transistor and the interconnect structure is another important factor for transistor performance. Keeping the contact resistance low increases signal transmission speeds while reducing power dissipation.
The threshold voltage and the contact resistance of integrated transistor devices are related to atomic, molecular, and crystalline properties of solid state materials used to form the source, drain, and channel regions. Thus, tuning the transistor performance generally involves adjusting material properties of the source and drain regions and of the channel region. Conventional methods of forming source and drain regions have focused on implanting dopant ions in the substrate and annealing the implantation damage to re-crystallize the doped regions. Doping profiles of the source and drain regions can be crafted in this way to influence the transistor threshold voltage. Gate oxide thickness and material properties have also been optimized to improve control of the threshold voltage. More recently, methods have been developed to increase charge carrier mobility within the channel region by imparting tensile or compressive stress to the channel. One way to stress the channel is to alter the gate stack. Another way of introducing stress in the channel is to form epitaxially grown raised source and drain regions, or epitaxially grown layers within the channel. As semiconductor technology nodes continue scaling down to smaller device dimensions, satisfying the requirement to achieve different threshold voltages (Vt) for different devices becomes extremely challenging, especially at gate lengths below 10 nm.
Transistor performance parameters such as threshold voltage and contact resistance fundamentally depend on the shape of the energy band structures at material interfaces between p-type and n-type materials within the device. Such interfaces are formed at the junction of the source region and the channel, at the junction of the drain region and the channel, and at metal contacts to the source and drain regions. Each semiconducting material on either side of an interface has a characteristic energy gap that represents the energy input needed to free electrons from the atoms, thus making available charge to conduct a current. An electric potential difference at the interface is overcome by applying a bias voltage that is equal to or greater than the threshold voltage.
The energy band structure of a thin film material is influenced by deposition methods and ambient conditions present during formation of the film. Techniques such as epitaxial growth and atomic layer deposition (ALD) attempt to control film deposition at molecular and atomic levels. Density function theory (DFT) studies familiar to the present inventor predict that the energy gap of a device that includes a molecular cluster thin film in which the cluster size is less than 1 nm will be determined by atomic orbital interactions within the molecules. Such effects of molecular clusters are described in the following journal papers by the present inventor, each of which is hereby incorporated by reference in its entirety: “Theoretical and Experimental Studies of Silver Bromide Clusters,” Doctoral dissertation by Hongguang Zhang, University of Texas at Arlington, 2000, hereinafter, “Zhang”; “Theoretical Study of the Molecular and Electronic Structures of Neutral Silver Bromide Clusters (AgBr) n, n=1-9,” H. Zhang, Z. A. Schelly, and D. S. Marynick, Journal of Physical Chemistry A, Jun. 10, 2000, vol. 104, pp. 6287-6294, hereinafter, “Zhang, et al.”; and “Preparation of AgBr Quantum Dots via Electroporation of Vesicles,” N. M. Correa, John H. Zhang, and Z. A. Schelly, Journal of the American Chemical Society, Jun. 23, 2000, vol. 122, pp. 6432-6434, hereinafter “Correa et al.” Also incorporated by reference in their entireties are the following related U.S. Patent documents to the present inventor: U.S. patent application Ser. No. 13/931,096, entitled, “Quantum Dot Array Devices with Metal Source and Drain,” filed Jun. 28, 2013; U.S. patent application Ser. No. 13/931,234, entitled “Threshold Adjustment for Quantum Dot Array Devices with Metal Source and Drain,” filed Jun. 28, 2013; and U.S. Patent Application Publication No. US2013/0093289, entitled “Size-controllable Opening and Method of Making Same,” filed Apr. 18, 2013.